BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 41; no. 7; pp. 2276 - 2289
• Main Authors: Mercier, Romain, Killian, Cedric, Kritikakou, Angeliki, Helen, Youri, Chillet, Daniel
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-07-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Approximate computing; bit-shuffling; Circuit faults; Computer Science; Data communication; fault mitigation; Fault tolerance; Fault tolerant systems; Faults; Hardware; Hardware Architecture; MBU; multiple faults; network-on-chip; Power demand; Redundancy; Routers; Routing; System on chip; Transistors
• DOI: 10.1109/TCAD.2021.3101406
• EISSN: 1937-4151
• ISSN: 0278-0070

Since several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in system-on-chip (SoC). Especially, faults occurring to the network-on-chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among intellectual properties (IPs). Furthermore, existing fault-tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the bit shuffling method (BiSuT) for fault-tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at runtime, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on least significant bits (LSBs), instead of keeping them on most significant bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to the existing approaches, like the Hamming code.