Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs
•A methodology is proposed to separate mobility of each level of stacked NW structure.•Lower low filed mobility is obtained for top GAA level comparing to Ω bottom NW.•Mobility varies with VB due to holes concentration reduction and displacement.•A linear behavior between mobility and back bias has...
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| Published in: | Solid-state electronics Vol. 149; pp. 62 - 70 |
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01-11-2018
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| Abstract | •A methodology is proposed to separate mobility of each level of stacked NW structure.•Lower low filed mobility is obtained for top GAA level comparing to Ω bottom NW.•Mobility varies with VB due to holes concentration reduction and displacement.•A linear behavior between mobility and back bias has been evidenced.•Mobility dependence on temperature remarkably varies with VB for Ω-NWs.
This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels. |
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| AbstractList | •A methodology is proposed to separate mobility of each level of stacked NW structure.•Lower low filed mobility is obtained for top GAA level comparing to Ω bottom NW.•Mobility varies with VB due to holes concentration reduction and displacement.•A linear behavior between mobility and back bias has been evidenced.•Mobility dependence on temperature remarkably varies with VB for Ω-NWs.
This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels. This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (I$_{DS}$) varying the back gate bias (V$_B$), aiming the extraction of carriers' mobility of each level separately. The methodology consists of three main steps and accounts for V$_B$ influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying V$_B$ through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V$_B$ for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of V$_B$ and up to 150°C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels. |
| Author | Vinet, Maud Barraud, Sylvain Pavanello, Marcelo Antonio Cassé, Mikaël Faynot, Olivier Paz, Bruna Cardoso Reimbold, Gilles |
| Author_xml | – sequence: 1 givenname: Bruna Cardoso surname: Paz fullname: Paz, Bruna Cardoso email: bcpaz@fei.edu.br organization: Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil – sequence: 2 givenname: Mikaël surname: Cassé fullname: Cassé, Mikaël organization: Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France – sequence: 3 givenname: Sylvain surname: Barraud fullname: Barraud, Sylvain organization: Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France – sequence: 4 givenname: Gilles surname: Reimbold fullname: Reimbold, Gilles organization: Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France – sequence: 5 givenname: Maud surname: Vinet fullname: Vinet, Maud organization: Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France – sequence: 6 givenname: Olivier surname: Faynot fullname: Faynot, Olivier organization: Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France – sequence: 7 givenname: Marcelo Antonio surname: Pavanello fullname: Pavanello, Marcelo Antonio organization: Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil |
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| Cites_doi | 10.1109/VLSIT.2016.7573416 10.1016/B978-012310675-9/50002-5 10.1109/TED.2014.2367574 10.1016/j.sse.2013.02.024 10.1109/IEDM.2008.4796805 10.1049/el:19880369 10.1109/LED.2012.2212691 10.1109/ULIS.2017.7962612 10.1109/16.337449 10.1016/j.sse.2007.07.019 10.1109/VLSIT.2012.6242437 10.1109/LED.2009.2027141 10.1109/IEDM.2016.7838441 10.1109/LED.2004.832786 10.1016/j.sse.2017.12.011 10.1109/S3S.2017.8309237 10.1016/j.mee.2013.09.016 10.1109/LED.2016.2637563 10.1109/ULIS.2012.6193351 10.1016/j.sse.2009.02.017 10.1016/j.sse.2013.01.033 10.1109/TED.2012.2231684 10.1109/TED.2012.2193129 |
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| Keywords | Mobility Temperature SOI Tridimensional numerical simulations Back gate bias Vertically stacked nanowires temperature back gate bias mobility tridimensional numerical simulations vertically stacked nanowires |
| Language | English |
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| References_xml | – volume: 141 start-page: 84 year: 2018 end-page: 91 ident: b0045 article-title: Electrical characterization of vertically stacked p-FET SOI nanowires publication-title: Solid-State Electron contributor: fullname: Cardoso Paz – volume: 25 start-page: 583 year: 2004 end-page: 585 ident: b0105 article-title: Improved split C-V method for effective mobility extraction in sub-0.1-µm Si MOSFET234-s publication-title: IEEE Electron Device Lett contributor: fullname: Ghibaudo – volume: 41 start-page: 2357 year: 1994 end-page: 2362 ident: b0115 article-title: On the universality of inversion layer mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration publication-title: IEEE Trans Electron Devices contributor: fullname: Tango – volume: 62 start-page: 224 year: 2015 end-page: 227 ident: b0095 article-title: Impact of the back-gate biasing on trigate MOSFET electron mobility publication-title: IEEE Trans Electron Devices contributor: fullname: Gámiz – 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volume: 38 start-page: 157 issue: 2 year: 2017 ident: 10.1016/j.sse.2018.08.012_b0070 article-title: Evidence of supercoupling effect in ultrathin silicon layers using a four-gate MOSFET publication-title: IEEE Electron Device Lett doi: 10.1109/LED.2016.2637563 contributor: fullname: Cristoloveanu – ident: 10.1016/j.sse.2018.08.012_b0010 doi: 10.1109/ULIS.2012.6193351 – volume: 53 start-page: 746 issue: 7 year: 2009 ident: 10.1016/j.sse.2018.08.012_b0055 article-title: Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET) publication-title: Solid-State Electron doi: 10.1016/j.sse.2009.02.017 contributor: fullname: Dupré – volume: 83 start-page: 10 year: 2013 ident: 10.1016/j.sse.2018.08.012_b0065 article-title: Mushroom-free selective epitaxial growth of Si, SiGe and SiGe: B raised sources and drains publication-title: Solid-State Electron doi: 10.1016/j.sse.2013.01.033 contributor: fullname: Hartmann – volume: 60 start-page: 727 issue: 2 year: 2013 ident: 10.1016/j.sse.2018.08.012_b0075 article-title: Strain-induced performance enhancement of trigate and omega-gate nanowire FETs scaled down to 10-nm width publication-title: IEEE Trans Electron Devices doi: 10.1109/TED.2012.2231684 contributor: fullname: Coquand – volume: 59 start-page: 1813 issue: 7 year: 2012 ident: 10.1016/j.sse.2018.08.012_b0015 article-title: Considerations for ultimate CMOS scaling publication-title: IEEE Trans Electron Dev doi: 10.1109/TED.2012.2193129 contributor: fullname: Kuhn |
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| Snippet | •A methodology is proposed to separate mobility of each level of stacked NW structure.•Lower low filed mobility is obtained for top GAA level comparing to Ω... This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a... |
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| SubjectTerms | Back gate bias Engineering Sciences Micro and nanotechnologies Microelectronics Mobility SOI Temperature Tridimensional numerical simulations Vertically stacked nanowires |
| Title | Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs |
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