Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 1; no. 4; pp. 510 - 518
• Main Authors: Xiaowu Zhang, Rajoo, R, Selvanayagam, C S, Premachandran, C S, Won Kyoung Choi, Soon Wee Ho, Siong Chiew Ong, Ling Xie, Pinjala, D, Dim-Lee Kwong, Yee Mong Khoo, Shan Gao
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01-04-2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Copper; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Joints; Low-temperature bonding; reliability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; stress; Studies; Tensile stress; through-silicon via; Through-silicon vias; Performance evaluation; stress; Thermal management (packaging); Failures; Mismatching; through-silicon via; Integrated circuit bonding; Thermal expansion; Low-temperature bonding; Tensile stress; Interconnection; Soldered joint; Integrated circuit; Cooling system; Silicon; Copper; Reliability; Room temperature; Crack; Via hole
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2011.2107511

Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints, comprised of completely of IMC compounds, will fail in a sudden unexpected manner as compared to normal solder joints, which fail in a ductile manner, where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress, during post-formation cooling down to room temperature, increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that, with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also been performed in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance than the samples with the conventional full pad design.