Design and integration considerations for end-of-the roadmap ultrashallow junctions

• Published in: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Vol. 18; no. 1; pp. 338 - 345
• Main Authors: Osburn, C. M., De, I., Yee, K. F., Srivastava, A.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: 01-01-2000
• Subjects: Capacitance; Computer simulation; MOSFET devices; Semiconductor doping
• DOI: 10.1116/1.591195
• EISSN: 1520-8567
• ISSN: 0734-211X

Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the 250–50 nm generations of complimentary metal-oxide-semiconductor ultralarge scale integration technology. The design of contacting and extension junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semiconductors off-state leakage specifications. A maxima in saturated drive current is observed for an intermediate extension junction depth (∼20 nm for 100 nm technology): shallower junctions lead to higher series resistance, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to depend on junction abruptness. For a perfectly abrupt junction, it is not necessary for the gate to overlap the junction. Performance depends on many parameters, including: overlap of gate to extension junction, junction capacitance, and parasitic series resistance, which depends on the doping gradient at the junction (spreading resistance), the extension series resistance, and the contact resistance. Extraction of these parameters using
I–V
or
C–V
measurements can potentially lead to erroneous conclusions about lateral junction excursion and abruptness.