An 80 ns 32K EEPROM using the FETMOS cell

• Published in: IEEE journal of solid-state circuits Vol. 17; no. 5; pp. 821 - 827
• Main Authors: Kuo, C., Yeargain, J.R., Downey, W.J., Ilgenstein, K.A., Jorvig, J.R., Smith, S.L., Bormann, A.R.
• Format: Journal Article
• Language: English
• Published: IEEE 01-10-1982
• Subjects: Costs; Dielectric devices; Dielectric substrates; Electron emission; Electron traps; EPROM; Nonvolatile memory; Testing; Tunneling; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1982.1051825

A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature sizes. The device has many built-in ease of use and ease of test features, including multimode erase (word, page, and bulk), bulk `O' program, latched inputs for program and erase operation, nonlocked high voltage supply, and margin test capability for both programmed and erased states. A unique TPP (transparent-partial programming) yield enhancement technique, using polysilicon fuse programming, can convert partially good 32K dice into totally good 16K and 8K devices.