An experimental 4-Mbit CMOS DRAM

• Published in: IEEE journal of solid-state circuits Vol. 21; no. 5; pp. 605 - 611
• Main Authors: Furuyama, T., Ohsawa, T., Watanabe, Y., Ishiuchi, H., Watanabe, T., Tanaka, T., Natori, K., Ozawa, O.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-10-1986; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Capacitors; Circuit testing; CMOS technology; DRAM chips; Electronics; Exact sciences and technology; Hot carriers; Integrated circuits; MOSFET circuits; Random access memory; Semiconductor device measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Size measurement; Voltage; Access time; Trench; Memory; Error rate; Electrical insulation; Dynamic conditions; Field effect transistor; Voltage converter; Random access memory(RAM); Complementary MOS technology; Integrated circuit; Irradiation; Reliability; Alpha particle
• DOI: 10.1109/JSSC.1986.1052584
• EISSN: 1558-173X
• ISSN: 0018-9200

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.