Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs

• Published in: IEEE transactions on electron devices Vol. 64; no. 5; pp. 2425 - 2431
• Main Authors: Grillet, Corentin, Logoteta, Demetrio, Cresti, Alessandro, Pala, Marco G.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Engineering Sciences; III–V materials; Indium arsenides; Ions; Logic gates; Micro and nanotechnologies; Microelectronics; MOSFETs; Nanowires; nanowires (NWs); nonequilibrium Green’s function (NEGF); ON-current; Performance degradation; Performance evaluation; Phonons; scaling; Scattering; Silicon; subthreshold swing; Surface roughness; surface roughness (SR); Tunneling; variability; scaling; nanowires (NWs); subthreshold swing; nonequilibrium Green’s function (NEGF); surface roughness (SR); III–V materials; variability; MOSFETs; ON-current
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2017.2679226

We present a numerical study aimed to benchmark short gate InAs nanowire-FETs (NW-FETs) against their strained Si (sSi) counterpart. Our full-quantum simulations focus on both gate-length scaling and device variability and include the impact of electron-phonon scattering and surface roughness (SR). Interestingly, we found that SR improves the subthreshold-voltage swing (SS) of short gate-length InAs devices by inducing a reduced source-to-drain tunneling. Hence, InAs NW-FETs exhibit a larger immunity to the roughness-induced degradation of the ON-current, whereas they suffer from a larger OFF-current and SS variability with respect to the sSi ones. According to our results, InAs NW-FETs could compete with sSi NW-FETs only for very short gate lengths, when the device performance is significantly degraded, while for longer devices sSi NW-FETs remain a more effective and reliable choice due to the higher gate overdrive charge.