Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution

• Published in: IEEE journal of solid-state circuits Vol. 36; no. 1; pp. 74 - 80
• Main Authors: Baechtold, P.H., Beakes, M.P., Buchmann, P., Clauberg, R., Ewen, J.F., Gilsdorf, J.F., Hauviller, P., Herkersdorf, A., Le Garrec, J.-C., Lemppenau, W., Parker, B., Pearson, D.J., Pereira, J.M., Plassat, D., reynolds, S.K., Schindler, H.R., Steimle, A., Webb, D.J., Widmer, A.X.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Add-drop multiplexers; Asynchronous transfer mode; Chips; Clocks; CMOS technology; Cost function; Digital; Framing; Hierarchies; Jitter; Multiplexing; Protection switching; Protocols; Serials; SONET; Synchronous; Synchronous digital hierarchy
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.896231

This paper presents a single-chip all-CMOS solution for 4/spl times/OC-3c, OC-12, and OC-12c synchronous digital hierarchy/synchronous optical network (SDH/SONET) framing with integrated serial line interfaces. Outstanding features of this chip are clock and data recovery and fulfillment of ITU-T and Bellcore jitter requirements for SDH/SONET systems, as well as the large range of functions offered. These functions include asynchronous transfer mode (ATM) and point-to-point protocol (PPP) support, as well as built-in native SDH/SONET functions such as digital cross-connect, add/drop multiplexing, and automatic protection switching. In addition, the chip is based on a new scalable modular architecture.