Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

• Published in: IEEE electron device letters Vol. 37; no. 9; pp. 1084 - 1087
• Main Authors: Kikuchi, Y., Chiarella, T., De Roest, D., Blanquart, T., De Keersgieter, A., Kenis, K., Peter, A., Ong, P., Van Besien, E., Tao, Z., Kim, M. S., Kubicek, S., Chew, S. A., Schram, T., Demuynck, S., Mocuta, A., Mocuta, D., Horiguchi, N.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-09-2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: anneal; Annealing; Bulk Si FinFET; Diffusion; Doping; FinFETs; Gates; Glass; Impurities; Logic gates; mobility; Phosphorus; PSG; Silicon; Silicon compounds; Silicon substrates; SiN; solid-source doping
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2016.2589661

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.