An Embedded All-Digital Circuit to Measure PLL Response

• Published in: IEEE journal of solid-state circuits Vol. 45; no. 8; pp. 1492 - 1503
• Main Authors: Fischette, Dennis M, Loke, Alvin L S, DeSantis, Richard J, Talbot, Gerry R
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-08-2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bandwidth; Circuit properties; Circuit testing; Circuits of signal characteristics conditioning (including delay circuits); CMOS integrated circuits; design- for-test; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; embedded test; Exact sciences and technology; Frequency estimation; Frequency measurement; Integrated circuits; loop response; measurement circuitry; peaking; Phase estimation; Phase locked loops; Phase measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; State estimation; State feedback; Testing, measurement, noise and reliability; Time measurement; Feedback regulation; design-for-test; Phase locking; Clock; Silicon on insulator technology; CMOS logic circuits; Complementary MOS technology; Bandwidth; embedded test; CMOS integrated circuits; phase-locked loops; Wafer; loop response; Closed loop; High performance; Arithmetic circuit; measurement circuitry; Frequency domain method; Design for testability; Step response; Phase locked loop; Time domain method; Integrated circuit; Digital circuit; Microprocessor; Divider; Gain; peaking
• DOI: 10.1109/JSSC.2010.2048143
• EISSN: 1558-173X
• ISSN: 0018-9200

We present an all-digital measurement circuit that enables wafer-level test and characterization of phase-locked loop (PLL) response. Through modifications only in the PLL feedback divider state machine, this technique facilitates accurate estimation of PLL frequency-domain closed-loop bandwidth and gain peaking by respectively measuring the time-domain crossover time and maximum overshoot of phase error to a self-induced phase step in the feedback clock. These transient measurements are related back to bandwidth and peaking through the proportionality relationships of crossover time to reciprocal bandwidth and maximum overshoot to peaking. The design-for-test circuit can be used to generate a transient plot of step response, measure static phase error, and observe phase-lock status. We report silicon results from two demonstration vehicles built in a 45-nm SOI-CMOS logic technology for high-performance microprocessors.