An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell

• Published in: IEEE journal of solid-state circuits Vol. 24; no. 5; pp. 1238 - 1243
• Main Authors: Momodomi, M., Itoh, Y., Shirota, R., Iwata, Y., Nakayama, R., Kirisawa, R., Tanaka, T., Aritome, S., Endoh, T., Ohuchi, K., Masuoka, F.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-10-1989; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Associate members; Character generation; Circuits; Electronics; EPROM; Exact sciences and technology; Flash memory; Integrated circuits; Integrated circuits by function (including memories and processors); Manufacturing; Nonvolatile memory; PROM; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Ultra large scale integration; Operation study; NAND circuit; EEPROM memory; Control circuit; Circuit design; Complementary MOS technology; Memory; Integrated circuit
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1989.572587

A 5-V-only high-density (512 K*8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a NAND-structured cell with 1.0- mu m design rules. The average cell area per bit is 12.9 mu m/sup 2/. Block erasing, successive programming, and random reading are achieved using a newly developed NAND-cell control circuit. Typical erasing time is 1.0 ms and page-programming time is 4.0 ms, equivalent to 1.0 mu s/bit. A dynamic sensing system is introduced to sense the small cell current. Typical read access time is 1.6 mu s. The die size is 10.7*15.3 mm/sup 2/.< >