Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing

• Published in: Journal of electronic testing Vol. 35; no. 5; pp. 741 - 759
• Main Authors: Maity, Dilip Kumar, Roy, Surajit Kumar, Giri, Chandan
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-10-2019; Springer Nature B.V
• Subjects: Algorithms; CAE) and Design; Circuits and Systems; Computer simulation; Computer-Aided Engineering (CAD; Defects; Electrical Engineering; Engineering; Integrated circuits; Interconnections; Optimization; Power consumption; Pre-bond testing; TSV test; Random defects; 3D IC; Clustered defects
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-019-05824-w

Three-dimensional Integrated Circuits (3D ICs) based on Through-Silicon Vias (TSVs) provide many benefits, such as high density, high bandwidth and low-power consumption. However, defects in TSV due to complex fabrication steps decrease the yield and reliability of 3D ICs. Therefore each die should be tested before it is stacked through pre-bond test. Pre-bond test and defect identification of TSVs are extremely important to screen out defective TSVs early in the manufacturing flow. Also, test cost minimization is one of the key issues of the testing process. The existing test time minimization solutions for pre-bond test consider random TSV defects. However, in practice clustered TSV faults are quite common. In this paper, we propose a novel test time minimization technique to address both random and clustered defect distributions. The proposed solutions are based on recursive bi-partitioning and padding of test sessions to minimize the number of required test sessions as well as test time. Simulation results show that the proposed method can achieve more than 50% reduction in test time for a 20-TSV network with four faulty TSVs compared to serial testing approach. The proposed algorithm also pinpoints the defective TSVs in a TSV network with a reduced test time compared to prior works.