Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs

• Published in: IEEE transactions on electron devices Vol. 53; no. 12; pp. 3110 - 3117
• Main Authors: Chandrasekaran, K., Xing Zhou, Siau Ben Chiah, Guan Huei See, Rustagi, S.C.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-12-2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Compact model; Compound structure devices; Electronics; Exact sciences and technology; heterostructure MOSFET; Poisson solution; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe; strained silicon (s-Si); surface potential; Transistors; Semiconductor alloys; MOSFET; Confinement; Scalability; Doping; Iterative method; Compact design; Modeling; heterostructure MOSFET; Buried channel; SiGe; Capacitance; Compact model; NMOS technology; Poisson solution; strained silicon (s-Si); Heterostructures; Surface potential
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.885520

A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces