An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

• Published in: IEEE journal of solid-state circuits Vol. 31; no. 9; pp. 1361 - 1363
• Main Authors: Maeda, T., Numata, K., Fujii, M., Tokushima, M., Wada, S., Fukaishi, M., Ishikawa, M.
• Format: Journal Article
• Language: English
• Published: IEEE 01-09-1996
• Subjects: Circuits; Clocks; Delay; Energy consumption; FETs; Flip-flops; Gallium arsenide; Latches; Switches; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.535426

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.