Low parasitic resistance contacts for scaled ULSI devices

• Published in: Thin solid films Vol. 332; no. 1-2; pp. 428 - 436
• Main Authors: OSBURN, C. M, BELLUR, K. R
• Format: Conference Proceeding Journal Article
• Language: English
• Published: Lausanne Elsevier Science 02-11-1998
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Parasitic behavior; ULSI circuit; Silicides; Doping; Contact resistance; Barrier height; Series resistance; Electrical characteristic; Self aligned technology
• ISSN: 0040-6090; 1879-2731
• DOI: 10.1016/S0040-6090(98)01046-3

Unless contact resistivity is reduced, the contact resistance ultimately becomes higher than the channel resistance and becomes useless in modern day devices. Several techniques, such as dielectric capping during junction annealing, are effective in reducing contact resistivity by maximizing interfacial dopant concentration and minimizing contact barrier heights. Silicides as diffusion sources is one solution which eliminates the interfacial dopant segregation. The use of elevated source drains (ESD) also allows the use of thicker silicides while minimizing the consumption-induced increase in contact resistivity. The use of heterojunction contacts using Si-Ge in the context of elevated source/drain is also another way to achieve low contact resistance.