Variability-tolerant routing algorithms for Networks-on-Chip

• Published in: Microprocessors and microsystems Vol. 38; no. 8; pp. 1037 - 1045
• Main Authors: Gawish, Eman Kamel, El-Kharashi, M. Watheq, Abu-Elyazeed, M.F.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01-11-2014
• Subjects: Networks-on-Chip (NoC); Process variations; Routing algorithms; Routing algorithms; Process variations; Networks-on-Chip (NoC)
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2014.08.002

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•Modifying XY, West-First, Negative-First, and Odd–Even algorithms to consider link failure probability when routing.•Proposing the NoC failure rate as a measure of tolerance against process-induced random and systematic delay variations.•Simulating NoC failure rate using a cyclic-accurate simulator under different technologies and traffic patterns.•Results show that as technology scales down, failure rate increases and traffic patterns have different failure rates.•Results show that variability-tolerant West-First routing achieves around 56% reduction in the overall NoC failure rate.
This paper proposes variability-tolerant routing algorithms for mesh-based Networks-on-Chip (NoC). Different NoC routing algorithms are modified, from variability perspective, to route flits through links with lower failure probability. The algorithms considered in this study are XY, West-First, Negative-First, and Odd–Even routing algorithms. To evaluate our variability-tolerant routing algorithms, a cycle-accurate simulator, NoCTweak, is used to measure how tolerant the resultant NoCs are against process variations. Results reflect the efficiency of our routing algorithms to overcome the process variation problems in modern fabrication technologies. For example, variability-tolerant West-First routing algorithm achieves up to 56% reduction in NoC overall failure rate.