A submicrometer CMOS embedded SRAM compiler

• Published in: IEEE journal of solid-state circuits Vol. 27; no. 3; pp. 417 - 424
• Main Authors: Tou, J.C., Gee, P., Duh, J., Eesley, R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-03-1992; Institute of Electrical and Electronics Engineers
• Subjects: Application specific integrated circuits; Applied sciences; CMOS technology; Density measurement; Design automation; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Packaging; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Synchronous generators; Testing; Timing; Velocity measurement; System architecture; Compiler; Random access memory(RAM); VLSI circuit; Complementary MOS technology; Performance characteristic; Modeling; Implementation
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.121565

A highly flexible memory generation system that produces high-density synchronous single- or dual-port static memories has been developed using a 0.7- mu m L/sub eff/ CMOS technology. The fully diffused memories are embedded into a gate-array environment. Configurations upwards of 1K words*256 b and 16K words*16 b have been obtained. Single-port address access times are, for example, 6.2 ns for 8K and 6.9 ns for 32K SRAMs. The Memorist SRAM Compiler provides for accurate timing characterization and is tightly integrated into an ASIC design CAD system. A gate-array-based test-chip cluster consisting of four 7.3*7.3 mm dies with 16 embedded diffused memories has also been developed.< >