Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 26; no. 4; pp. 645 - 658
• Main Authors: Zhuoyuan Li, Hong, X., Qiang Zhou, Shan Zeng, Bian, J., Wenjian Yu, Yang, H.H., Pitchumani, V., Chung-Kuan Cheng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-04-2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computer science; Constraints; Delay; Design automation; Design optimization; Dynamical systems; Dynamics; Floorplanning; INT; Integrated circuit interconnections; Integrated circuit technology; Interlayers; Mathematical models; Optimization; Programming; Studies; Temperature; thermal; Thermal conductivity; Thermal resistance; Very large scale integration; very large scale integration (VLSI)
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2006.885831

In this paper, we investigate thermal via (T-via) planning during three-dimensional (3-D) floorplanning. First, we consider the temperature constrained T-via planning (TVP) problem on a given 3-D floorplan. Second, we integrate dynamic TVP into 3-D floorplanning process. Our main contribution and results can be summarized as follows. We solve the temperature constrained TVP problem by solving a sequence of simplified interlayer and intralayer TVP subproblems. Each subproblem is formulated as convex programming problem and we derive nearly optimal solution for detailed T-via distribution. Based on the TVP solution, we implement the integrated TVP and 3-D floorplanning algorithm in a two-stage approach. Before floorplanning, blocks are assigned into different layers by solving a sequence of knapsack problems. During floorplanning, T-vias are allocated with white space redistribution to optimize T-via insertion. Experimental results show that our TVP approach can reduce T-vias by 12% compared with a recent published work (J. Cong and Y. Zhang, "Thermal via planning for 3-D ICs," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2005, pp.745-752). Compared with the postfloorplanning optimization approach, integrating TVP into floorplanning process can reduce T-vias by 16% with 21% runtime overhead