A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

• Published in: IEEE journal of solid-state circuits Vol. 25; no. 1; pp. 42 - 47
• Main Authors: Furuyama, T., Ishiuchi, H., Tanaka, H., Watanabe, Y., Kohyama, Y., Kimura, T., Muraoka, K., Sugiura, S., Natori, K.
• Format: Journal Article
• Language: English
• Published: IEEE 01-02-1990
• Subjects: Character generation; DRAM chips; Failure analysis; Hysteresis; Power engineering and energy; Power generation; Random access memory; Read-write memory; Transistors; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.50282

A latch-up-like failure phenomenon that shows hysteresis in the V/sub cc/-I/sub cc/ characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor.< >