A high-density NAND EEPROM with block-page programming for microcomputer applications

• Published in: IEEE journal of solid-state circuits Vol. 25; no. 2; pp. 417 - 424
• Main Authors: Iwata, Y., Momodomi, M., Tanaka, T., Oodaira, H., Itoh, Y., Nakayama, R., Kirisawa, R., Aritome, S., Endoh, T., Shirota, R., Ohuchi, K., Masuoka, F.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-04-1990; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Associate members; Circuit testing; CMOS memory circuits; Costs; Electronics; EPROM; Equivalent circuits; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Microcomputers; Nonvolatile memory; Portable computers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Threshold voltage; Resonant tunnel effect; NAND circuit; EEPROM memory; Circuit design; High density; Complementary MOS technology; Test; Memory; Logic gate; MOS transistor; Experimental study; Microcomputer
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.52165

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption.< >