An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer

• Published in: IEEE journal of solid-state circuits Vol. 58; no. 4; pp. 929 - 938
• Main Authors: Lee, Seungjong, Kang, Taewook, Song, Seungheun, Kwon, Kyumin, Flynn, Michael P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-04-2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-to-digital converter (ADC); Bandwidth; Capacitors; continuous-time (CT) sigma-delta modulator (SDM); Delays; Feedback loops; Figure of merit; hybrid ADC; noise-shaping (NS); Prototypes; Quantization (signal); Registers; Signal resolution; Signal to noise ratio; successive approximation register (SAR); time-interleaving (TI)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3228760

This work introduces a time-interleaved architecture to tackle the speed-resolution bottleneck of the noise-shaping (NS) successive approximation register (SAR) quantizer in a continuous-time (CT) sigma-delta modulator (SDM). A critical insight is that introducing a delay in the NS quantizer feedback loop enables complete parallelization of the NS quantizer operations. The extra time from parallelization greatly relaxes loop filtering and residue integration and enables a high quantizer resolution. Furthermore, the extra time in the feedback loop allows data weighted averaging (DWA), which eliminates the need for calibration. The prototype comprises a second-order CT front-end and a fully interleaved first-order NS quantizer. The prototype is fabricated in a 28 nm process, occupies 0.072 mm2 and consumes 6.4 mW. The peak signal-to-noise ratio (SNR), signal-to-noise-distortion ratio (SNDR), and dynamic range (DR) are 83.9, 81.6, and 84.8 dB, respectively, in a 15.625 MHz bandwidth. The corresponding Schreier SNDR figure of merit (FoM) is 175.5 dB.