A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 11; pp. 3839 - 3852
• Main Authors: De Caro, Davide, Di Meo, Gennaro, Napoli, Ettore, Petra, Nicola, Strollo, Antonio Giuseppe Maria
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clock generators; Clocks; Clocks & watches; CMOS; delay interpolator; Delay lines; Digital electronics; digitally controlled delay-line; Domains; Electromagnetic interference; Electromagnetic noise; EMI reduction; Frequency modulation; modulation profile; Noise reduction; Phase locked loops; Power consumption; Spread spectrum; Spread spectrum transmission; Spread-spectrum clock generator (SSCG); Synchronism; Synchronization; synchronization constraint; Time synchronization; Waveforms
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.3008481

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm 2 , whereas power consumption is 48.5mW in double output mode and 34mW in single output mode.