Interface Traps in InAs Nanowire Tunnel FETs and MOSFETs-Part II: Comparative Analysis and Trap-Induced Variability

• Published in: IEEE transactions on electron devices Vol. 60; no. 9; pp. 2802 - 2807
• Main Authors: Esseni, David, Pala, Marco G.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-09-2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Capacitance; Cross-disciplinary physics: materials science; rheology; Electronics; Exact sciences and technology; Logic gates; Materials science; MOSFET; Nanoscale devices; Nanoscale materials and structures: fabrication and characterization; nanowire; NEGF; phonon scattering; Physics; quantum transport; Quantum wires; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; traps; tunnel-FET; Tunneling; MOS technology; MOSFET; Voltage current curve; Oxide layer; Random distribution; tunnel-FET; Degradation; Thickness; Field effect transistor; traps; NEGF; Nanowire device; Nanowires; Phonon scattering; Quantum transport; Damaging; nanowire
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2274197

This paper extends the analysis of the companion paper by presenting a comparative analysis of the impact of interface traps on the I-V characteristics of InAs nanowire tunnel FETs or MOSFETs with a spatially random distribution of traps. The physical mechanisms behind the effects of traps in either tunnel FETs or MOSFETs are compared and, furthermore, traps are also investigated as a possible source of device variability. Our results show that, in MOSFETs, an aggressive oxide thickness scaling can effectively counteract the degradation of the subthreshold slope (SS) possibly produced by interface traps. Tunnel FETs are instead more vulnerable to traps, which are probably the main hindrance to the experimental realization of tunnel FETs with an SS better than 60 mV/decade.