A 4-MHz Digitally Controlled Voltage-Mode Buck Converter With Embedded Transient Improvement Using Delay Line Control Techniques

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 11; pp. 4029 - 4040
• Main Authors: Huang, Qiwei, Zhan, Chenchang, Burm, Jinwook
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buck converters; Clocks; CMOS; dc-dc converter; Delay lines; Delay time; delay-line-based; Delays; digital pulse width modulation (DPWM); digital type-II compensator; Digitally controlled buck converter; Electric potential; Frequency dividers; Phase detectors; Pulse duration; time-based; Transient analysis; transient improvement; Transient response; Voltage; Voltage control; Voltage measurement; voltage-mode control; voltage-to-delay
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.3012014

In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL's) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard <inline-formula> <tex-math notation="LaTeX">0.18~\mu \text{m} </tex-math></inline-formula> CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than <inline-formula> <tex-math notation="LaTeX">16~\mu \text{s} </tex-math></inline-formula>. The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage.