2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory

• Published in: IEEE journal of solid-state circuits Vol. 57; no. 4; pp. 1125 - 1137
• Main Authors: Seo, Min-Woong, Chu, Myunglae, Jung, Hyun-Yong, Kim, Suksan, Song, Jiyoun, Bae, Daehee, Lee, Sanggwon, Lee, Junan, Kim, Sung-Yong, Lee, Jongyeon, Kim, Minkyung, Lee, Gwi-Deok, Shim, Heesung, Um, Changyong, Kim, Changhwa, Baek, In-Gyu, Kwon, Doowon, Kim, Hongki, Choi, Hyuksoon, Go, Jonghyun, Ahn, Jungchak, Lee, Jae-Kyu, Moon, Chang-Rok, Lee, Kyupil, Kim, Hyoung-Sub
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-04-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Analog to digital converters; Capacitors; Circuit design; CMOS; CMOS image sensor (CIS); digital pixel sensor (DPS); Dynamic random access memory; Frames per second; global shutter (GS); High speed; Integrated circuit interconnections; low random noise (RN); low-power consumption; pixel-level analog-to-digital converter (ADC); Pixels; Power consumption; Power demand; Random access memory; Random noise; Sensor arrays; Sensors; Substrates; Transistors; Wideband
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3142436

This article presents a low random noise, a low-power, and a high-speed 2-mega pixels (Mp) global-shutter (GS)-type CMOS image sensor (CIS) using an advanced dynamic random access memory (DRAM) technology. GS CIS is one of the alternatives to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-D image data can be simultaneously sampled by the in-pixel analog memory. To achieve a high-performance GS CIS, we proposed a novel architecture for digital pixel sensor (DPS) which is a high-speed GS operation CIS with a pixel-wise analog-to-digital converter (ADC) and an in-pixel digital memory. The major technologies of the proposed DPS can be summarized as follows: 1) two large coupling capacitors with mature DRAM technology; 2) extremely narrow pitch Cu-to-Cu (C2C) bond; and 3) finally low-powered ADC with a near sub-threshold operation. A perfect auto-zero operation for ADC is implemented using two DRAM capacitors, and a large number of transistors have to be integrated in the single pixel for realizing pixel-level ADC. Thus, each pixel has two fine-pitch C2C interconnections. This makes it possible to realize wafer-level stacked unit pixel. The proposed DPS with low-power consuming analog circuits has been successfully designed and developed for extremely fast-readout speed of max. 1200 frames per second (fps) and high sensitivity for low-illumination conditions.