A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology
In recent years, the size of transistors has been scaled down to a few nanometers and further shrinking will eventually reach the atomic scale. Monolithic three-dimensional (M3D) ICs use the third dimension for placement and routing, which helps reduce footprint and improve power and performance of...
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Published in: | IEEE MICRO Vol. 39; no. 6; pp. 38 - 45 |
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01-11-2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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Abstract | In recent years, the size of transistors has been scaled down to a few nanometers and further shrinking will eventually reach the atomic scale. Monolithic three-dimensional (M3D) ICs use the third dimension for placement and routing, which helps reduce footprint and improve power and performance of circuits without relying on technology shrinking. This article explores the benefits of M3D ICs using OpenPiton, a scalable open-source Reduced Instruction Set Computer (RISC)-V-based multicore SoC. With a logic-on-memory 3-D integration scheme, we analyze the power and performance benefits of two OpenPiton single-tile systems with smaller and larger memory architectures. The logic-on-memory M3D design shows 36.8% performance improvement compared to the corresponding tile design in 2-D. In addition, at isoperformance, M3D shows 13.5% total power saving. |
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AbstractList | In recent years, the size of transistors has been scaled down to a few nanometers and further shrinking will eventually reach the atomic scale. Monolithic three-dimensional (M3D) ICs use the third dimension for placement and routing, which helps reduce footprint and improve power and performance of circuits without relying on technology shrinking. This article explores the benefits of M3D ICs using OpenPiton, a scalable open-source Reduced Instruction Set Computer (RISC)-V-based multicore SoC. With a logic-on-memory 3-D integration scheme, we analyze the power and performance benefits of two OpenPiton single-tile systems with smaller and larger memory architectures. The logic-on-memory M3D design shows 36.8% performance improvement compared to the corresponding tile design in 2-D. In addition, at isoperformance, M3D shows 13.5% total power saving. |
Author | Zhu, Lingjun Pentapati, Sai Garcia-Ortiz, Alberto Bamberg, Lennart Lim, Sung Kyu Shim, Da Eun |
Author_xml | – sequence: 1 givenname: Sai surname: Pentapati fullname: Pentapati, Sai organization: Georgia Institute of Technology – sequence: 2 givenname: Lingjun surname: Zhu fullname: Zhu, Lingjun email: lingjun@gatech.edu organization: Georgia Institute of Technology – sequence: 3 givenname: Lennart surname: Bamberg fullname: Bamberg, Lennart email: bamberg@item.uni-bremen.de organization: University of Bremen – sequence: 4 givenname: Da Eun surname: Shim fullname: Shim, Da Eun email: daeun@gatech.edu organization: Georgia Institute of Technology – sequence: 5 givenname: Alberto surname: Garcia-Ortiz fullname: Garcia-Ortiz, Alberto email: agarcia@item.uni-bremen.de organization: University of Bremen – sequence: 6 givenname: Sung Kyu surname: Lim fullname: Lim, Sung Kyu email: limsk@ece.gatech.edu organization: Georgia Institute of Technology |
BookMark | eNo9kM9PwjAUxxuDiYCePXhZ4rnQvnZrdySgYrJFEzEem628wQis2I7D_ntHIJ7ej3y-75v3HZFB4xok5JGzCecsneb5BBhPJ5BKKQS7IUOeCkUll2JAhgwUUK4E3JFRCDvGWAxMD8lyFmVuU1vqGprjwfku-vTOYgjO068utHiIFhjqTRP91O02yl3j9n1T20jQRbRCu-0XbtPdk9uq2Ad8uNYx-X59Wc2XNPt4e5_PMmpBpy1FhrIsRCHiquQsAUhKlSRSA3ILEsR6XSXIi8IqycqytAJiFSuh-yHWcZKKMXm-3D1693vC0JqdO_mmtzQguFAa-u97anqhrHcheKzM0deHwneGM3OOy-S5OcdlrnH1iqeLokbEf1rrmAOk4g_xXGW- |
CODEN | IEMIDZ |
CitedBy_id | crossref_primary_10_3390_electronics10161930 crossref_primary_10_1145_3473462 crossref_primary_10_1109_TCPMT_2022_3221025 crossref_primary_10_1109_TVLSI_2021_3073070 |
Cites_doi | 10.1007/978-1-4419-9542-1_20 10.1038/s41586-018-0855-y 10.1109/HPCA.2010.5416628 10.1109/TCAD.2017.2648839 10.1109/IEDM.2014.7047120 10.1145/2872362.2872414 |
ContentType | Journal Article |
Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019 |
Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019 |
DBID | 97E RIA RIE AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D |
DOI | 10.1109/MM.2019.2944330 |
DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE All-Society Periodicals Package (ASPP) 1998-Present IEEE Electronic Library Online CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional |
DatabaseTitle | CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Professional |
DatabaseTitleList | Technology Research Database |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library Online url: http://ieeexplore.ieee.org/Xplore/DynWel.jsp sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Computer Science |
EISSN | 1937-4143 |
EndPage | 45 |
ExternalDocumentID | 10_1109_MM_2019_2944330 8851229 |
Genre | orig-research |
GrantInformation_xml | – fundername: Defense Advanced Research Projects Agency grantid: HR001118C0096 funderid: 10.13039/100000185 |
GroupedDBID | -DZ -~X .DC 0R~ 29I 3EH 4.4 5GY 5VS 6IK 97E AAJGR AASAJ AAYOK ABQJQ ABVLG ACGFO ACGFS ACGOD ACIWK ACNCT AENEX AETEA AETIX AI. AIBXA AKJIK ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV AZLTO BEFXN BFFAM BGNUA BKEBE BKOMP BPEOZ C1A CS3 DU5 EBS EJD HZ~ H~9 IBMZZ ICLAB IEDLZ IFIPE IFJZH IPLJI JAVBF LAI M43 MS~ O9- OCL OHT P2P PQQKQ RIA RIC RIE RIG RNI RNS RZB TAE TN5 TWZ VH1 XFK YZZ ZCG AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D |
ID | FETCH-LOGICAL-c289t-e0e4ba3a35fb106226b766482e1c2423ddf6e1aac740bbbc325757380bb585693 |
IEDL.DBID | RIE |
ISSN | 0272-1732 |
IngestDate | Thu Oct 10 16:53:05 EDT 2024 Thu Sep 26 19:49:03 EDT 2024 Wed Jun 26 19:31:24 EDT 2024 |
IsPeerReviewed | true |
IsScholarly | true |
Issue | 6 |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-c289t-e0e4ba3a35fb106226b766482e1c2423ddf6e1aac740bbbc325757380bb585693 |
PQID | 2313782433 |
PQPubID | 37061 |
PageCount | 8 |
ParticipantIDs | proquest_journals_2313782433 crossref_primary_10_1109_MM_2019_2944330 ieee_primary_8851229 |
PublicationCentury | 2000 |
PublicationDate | 2019-11-01 |
PublicationDateYYYYMMDD | 2019-11-01 |
PublicationDate_xml | – month: 11 year: 2019 text: 2019-11-01 day: 01 |
PublicationDecade | 2010 |
PublicationPlace | Los Alamitos |
PublicationPlace_xml | – name: Los Alamitos |
PublicationTitle | IEEE MICRO |
PublicationTitleAbbrev | MM |
PublicationYear | 2019 |
Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
References | chang (ref10) 0 ref8 yadav (ref2) 2019; 565 brunet (ref4) 0 ref3 ref6 ref5 (ref7) 0 ref1 ku (ref9) 0 |
References_xml | – year: 0 ident: ref7 article-title: High bandwidth memory – start-page: 1 year: 0 ident: ref4 article-title: First demonstration of a CMOS over CMOS 3-D VLSI CoolCube™ integration on 300 mm wafers publication-title: Proc IEEE Symp VLSI Technol contributor: fullname: brunet – ident: ref6 doi: 10.1007/978-1-4419-9542-1_20 – volume: 565 start-page: 468 year: 2019 ident: ref2 article-title: Spatially resolved steady-state negative capacitance publication-title: Nature doi: 10.1038/s41586-018-0855-y contributor: fullname: yadav – start-page: 90 year: 0 ident: ref9 article-title: Compact-2-D: A physical design methodology to build commercial-quality face-to-face-bonded 3-D ICs publication-title: Proc Int Symp Phys Design contributor: fullname: ku – ident: ref5 doi: 10.1109/HPCA.2010.5416628 – start-page: 1 year: 0 ident: ref10 article-title: Cascade2-D: A design-aware partitioning approach to monolithic 3-D IC with 2-D commercial tools publication-title: Proc IEEE/ACM Int Conf Comput -Aided Design contributor: fullname: chang – ident: ref8 doi: 10.1109/TCAD.2017.2648839 – ident: ref1 doi: 10.1109/IEDM.2014.7047120 – ident: ref3 doi: 10.1145/2872362.2872414 |
SSID | ssj0005208 |
Score | 2.34885 |
Snippet | In recent years, the size of transistors has been scaled down to a few nanometers and further shrinking will eventually reach the atomic scale. Monolithic... |
SourceID | proquest crossref ieee |
SourceType | Aggregation Database Publisher |
StartPage | 38 |
SubjectTerms | Computer architecture Delays Energy conservation Instruction sets (computers) Integrated circuits Logic Microprocessors RISC Routing Systems design Three-dimensional displays Transistors Two dimensional displays Wires |
Title | A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology |
URI | https://ieeexplore.ieee.org/document/8851229 https://www.proquest.com/docview/2313782433 |
Volume | 39 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwELVoJxYKFEShIA8MDLhNbCe2x4q26hIWQLBFsXNWu6SoHwP_HttJSyVY2OIojqIXn_3OfneH0D1Qm0RWcMILa5yDIoEoLY2zK5CliSBKtI93nr2I5w85nvg0OY_7WBgACOIzGPjLcJZfLs3Wb5UNpaMHlKoWagkl61itQzlHmHWpoCQWjDZpfOJIDbPMS7jUgCrOmZc7H6xAoaTKr3k4LC7Tzv8-6xSdNCQSj-q_foaOoDpHnV2BBtzYaxfNRtjXUjZkWZHMS2q_cBMYsFyROlc5HgcJB35fbObYGbiXw80XBjMyxj_b7hfobTp5fZqRpnQCMc6D2hCIgOuCFSyx2jl9jmNpkaZcUoiNZ1BlaVOIi8IIHmmtDXOWmwgmXcP5D6lil6hdLSu4QtgXsjHuvgCRcEuVTIvEWg2WpzqJ06SHHnZw5p91how8eBaRyrMs98jnDfI91PXo7R9rgOuh_g7-vLGgde54J3PsxXW7_rvXDTr2767jAvuovVlt4Ra11uX2LoyMb7NItUc |
link.rule.ids | 315,782,786,798,27933,27934,54767 |
linkProvider | IEEE |
linkToHtml | http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwED1BGWChQEEUCnhgYMBt4o84GSvaqgjCQhFsUeycBUuLoB3499hJWirBwhZHsRK9-Ox39rs7gEtkVgZWCSpya5yDEiNNdGycXWFcmAADqX288_hRPbzEg6FPk3O9ioVBxFJ8hl1_WZ7lFzOz8FtlvdjRA8aSTdiSQkWqitZaF3SU8y5TjIaKszqRTxgkvTT1Iq6kyxIhuBc8r61BZVGVXzNxubyMmv_7sD3YrWkk6Vf_fR82cHoAzWWJBlJbbAvGfeKrKRs6m9LUi2q_SB0aMPugVbZyMihFHOT5bf5KnIl7QdzrmyGcDsjPxvshPI2Gk5sxrYsnUON8qDnFAIXOec6l1c7tcyxLqygSMcPQeA5VFDbCMM-NEoHW2nBnu1Lx2DWcBxEl_Aga09kUj4H4UjbG3VeopLAsiaNcWqvRikjLMJJtuFrCmb1XOTKy0rcIkixNM498ViPfhpZHb_VYDVwbOkv4s9qGPjPHPLnjL67byd-9LmB7PEnvs_vbh7tT2PHvqaIEO9CYfyzwDDY_i8V5OUq-AW54uJg |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+Logic-on-Memory+Processor-System+Design+With+Monolithic+3-D+Technology&rft.jtitle=IEEE+MICRO&rft.au=Pentapati%2C+Sai&rft.au=Zhu%2C+Lingjun&rft.au=Bamberg%2C+Lennart&rft.au=Shim%2C+Da+Eun&rft.date=2019-11-01&rft.pub=IEEE&rft.issn=0272-1732&rft.eissn=1937-4143&rft.volume=39&rft.issue=6&rft.spage=38&rft.epage=45&rft_id=info:doi/10.1109%2FMM.2019.2944330&rft.externalDocID=8851229 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0272-1732&client=summon |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0272-1732&client=summon |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0272-1732&client=summon |