Approximate Full-Adders: A Comprehensive Analysis

• Published in: IEEE access Vol. 12; pp. 136054 - 136072
• Main Authors: Napoli, Ettore, Zacharelos, Efstratios, Strollo, Antonio G. M., Di Meo, Gennaro
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Adding circuits; Approximate computing; approximate full adders; Arithmetic; binary adders; binary multipliers; Circuit synthesis; Circuits; Digital arithmetic; Error analysis; Image processing; Logic; Synthesis; Transistors; Video
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3463182

Approximate computing is a technique that sacrifices the accuracy of the result for an advantage in terms of power, area, and speed. It is useful for error-tolerant applications such as image and video processing. Many approximate arithmetic circuits can be devised using approximate versions of the basic binary full adder that simply adds three bits to generate carry and sum. Therefore, the approximate full adder has been the subject of extensive investigation in recent years. In this paper we present a comprehensive analysis of approximate full adders, by synthesizing in a FinFET 14 nm technology the whole set of possible designs, achievable by modifying one or more entries of the full adder truth-table. Our exhaustive analysis shows that only a few out of the many thousands of synthesized circuits perform reasonably well as approximate full adders. Our analysis re-discovers the approximate full adders already proposed in the literature and identifies some new ones. Examples of using the newly discovered approximate full adders in typical error resilient applications are provided, showing the performance and the usefulness of approximate arithmetic circuit designs in the real-world.