Characterization Challenges of a Low Noise Charge Detection ROIC

• Published in: IEEE transactions on instrumentation and measurement Vol. 71; pp. 1 - 8
• Main Authors: Mohammad Zaki, Alireza, Nihtianov, Stoyan
• Format: Journal Article
• Language: English
• Published: New York IEEE 2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Characterization; Circuit design; Data acquisition; Detectors; double-threshold technique; Error analysis; Field programmable gate arrays; Integrated circuits; Low noise; low power; Narrowband; Noise; Pins; Power consumption; Programming; readout front end; Shape; wideband
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2022.3160529

This article presents the experimentally characterized performance of a low noise and wideband sensor readout integrated circuit (ROIC). The ROIC is designed to detect small amounts of charge generated by a silicon p-i-n detector as a result of particle detection, with very high time resolution and limited power consumption. The architecture of the ROIC permits the analog components of the particle readout to be designed with a reduced bandwidth by implementing the so-called intersymbol interference (ISI) cancellation technique, which improves the noise performance, while reducing the deterministic ISI-induced errors associated with the narrowband circuit; hence, a low error rate (ER) can be maintained. The readout is designed to detect 160 aC charge portions delivered randomly by the detector at a maximum of <inline-formula> <tex-math notation="LaTeX">4 \times 10^{8} </tex-math></inline-formula> events/s with a small average ER while consuming 2.85 mW. Detailed information about the ROIC designed in 65-nm CMOS technology, and the simulated performance, are already reported in a previous publication. This article aims to present the challenges related to the design of the test setup and the obtained experimental results with the first prototype of the ROIC, as well as to discuss the data acquisition process.