Low-Loss and Compact Bends on Multi-Layer SiN-on-SOI Platform for Photonic Integrated Circuits

Low-loss, compact silicon nitride and silicon waveguide bends are demonstrated using COMS-compatible multi-layer PECVD SiN-on-SOI integration platform over the whole C band. The curvature of advanced waveguide bend is designed with linearly changing to reduce bending loss. The bending loss for PECVD...

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Bibliographic Details
Published in:IEEE photonics technology letters Vol. 33; no. 20; pp. 1131 - 1134
Main Authors: Gao, F., Xie, W., Li, B., Bu, X., Song, A., Luo, X., Lo, G.-Q.
Format: Journal Article
Language:English
Published: New York IEEE 15-10-2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:Low-loss, compact silicon nitride and silicon waveguide bends are demonstrated using COMS-compatible multi-layer PECVD SiN-on-SOI integration platform over the whole C band. The curvature of advanced waveguide bend is designed with linearly changing to reduce bending loss. The bending loss for PECVD SiN reduces from 0.087 dB/90° for normal bend to 0.037 dB/90° for advanced bend with the radius of <inline-formula> <tex-math notation="LaTeX">30~\mu \text{m} </tex-math></inline-formula>. It indicates a 60% footprint reduction with same loss level compared with the normal bend with 50-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> radius. Wafer-level distribution and uniformity of the bending loss are characterized, showing the stable performance. Similarly, we demonstrate a <inline-formula> <tex-math notation="LaTeX">3~\mu \text{m} </tex-math></inline-formula>-radius silicon waveguide bend in the same platform, showing the bending loss of only 0.0065 dB/90° bending loss, which is even smaller comparing to 0.012 dB/90° bend loss of a <inline-formula> <tex-math notation="LaTeX">5~\mu \text{m} </tex-math></inline-formula>-radius normal bend. Such advanced bend design with significantly reduced loss and footprint paves a way for high-dense large-scale photonic integrated circuits.
ISSN:1041-1135
1941-0174
DOI:10.1109/LPT.2021.3107865