A VHDL fault diagnosis tool using functional fault models

• Published in: IEEE design & test of computers Vol. 9; no. 2; pp. 33 - 41
• Main Authors: Pitchumani, V., Mayor, P., Radia, N.
• Format: Journal Article
• Language: English
• Published: IEEE Computer Society 01-06-1992
• Subjects: Algorithm design and analysis; Circuit analysis; Circuit faults; Circuit testing; Dictionaries; Fault diagnosis; Hardware; Latches; Logic testing; Sequential circuits
• ISSN: 0740-7475; 1558-1918
• DOI: 10.1109/54.143144

The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault diagnosis tool (VFDT) are discussed. Given a VHDL description, a compiler creates an internal representation suitable for simulation and fault diagnosis. VFDT diagnoses faults in this representation hierarchically using the stuck-at fault model at the first level and the arbitrary-failure model at the second level. It reasons from first principles by means of constraint suspension. Examples of fault diagnosis using the VFDT are described.< >