A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

• Published in: IEEE journal of solid-state circuits Vol. 31; no. 2; pp. 240 - 246
• Main Authors: Maeda, T., Numata, K., Tokushima, M., Ishikawa, M., Fukaishi, M., Hida, H., Ohno, Y.
• Format: Journal Article
• Language: English
• Published: IEEE 01-02-1996
• Subjects: Analytical models; Circuit analysis; Circuit synthesis; Degradation; Delay; Driver circuits; Flip-flops; Gallium arsenide; Heterojunctions; Low voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.488001

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.