Optimized retrograde N-well for 1-μm CMOS technology

Optimized retrograde N-well for 1-μm CMOS technology

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Bibliographic Details
Published in:IEEE journal of solid-state circuits Vol. 21; no. 2; pp. 286 - 292
Main Authors: MARTIN, R. A, CHEN, J. Y.-T
Format: Journal Article
Language:English
Published: New York, NY Institute of Electrical and Electronics Engineers 01-04-1986
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Ion implantation
VLSI circuit
Impurity density
Spurious capacity
Digital simulation
Well
Ionic kinetic energy
Phosphorus
Transistor
N type conductivity
Epitaxial film
Optimization
Thickness
Microelectronic fabrication
Complementary MOS technology
Integrated circuit
Multiplier
Leakage current
Silicon
Delay time
Performance
Dose
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Description
ISSN:0018-9200
1558-173X
DOI:10.1109/jssc.1986.1052516