Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement

• Published in: IEEE transactions on electron devices Vol. 64; no. 8; pp. 3498 - 3501
• Main Authors: Chiu, Yu-Chien, Cheng, Chun-Hu, Liou, Guan-Lin, Chang, Chun-Yen
• Format: Journal Article
• Language: English
• Published: IEEE 01-08-2017
• Subjects: Capacitance; Charge trpapping; Dielectrics; ferroelectric; Logic gates; multilevel; nonvolatile memory; Random access memory; Switches; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2017.2712709

In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <;1fA/μm and >10 8 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by ±5 V under 20-ns speed for a long endurance cycling (~10 12 cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.