A multi‐objective optimization approach for modeling and analyzing the impact of drive parameters in SiC power converters

• Published in: International journal of circuit theory and applications Vol. 52; no. 10; pp. 5107 - 5122
• Main Authors: Liu, Xinbo, Liu, Bo, He, Shuiyuan, Ma, Ruiqi, Diao, Lijun
• Format: Journal Article
• Language: English
• Published: Bognor Regis Wiley Subscription Services, Inc 01-10-2024
• Subjects: Design optimization; drive parameters; Impact analysis; influence mechanism model; multi‐objective optimization; Optimization models; Parameters; Pareto solution; Power converters; SiC converters; Silicon carbide
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.4003

Summary
This paper introduces an equivalent model including the parasitic parameters analysis of silicon carbide (SiC) MOSFETs in order to enhance their performance for high‐power density applications. The model is used to establish a mechanism that evaluates the effect of drive parameters on switching losses and electrical stress of power devices, providing a theoretical basis for optimizing the design of drive parameters. The paper finds the Pareto solution of the multi‐objective optimization model through iterative calculation of design variables, using this mechanism. The methodology is validated through experimental results from an SiC power prototype, showing an efficiency of 98.9% and safe electrical stress levels under 1500 V/100 kW operating conditions.
During iterations, as the efficiency constraint increases, the efficiency constraint of the previous iteration is the maximum efficiency that the converter can achieve when no results exist. Meanwhile, the current change rate and the corresponding driving parameters can be obtained. Based on the slope of the current change rate and the efficiency, the Pareto solution can be divided into three areas. Among them, Areas 2 and 3 have a more obvious efficiency improvement than Area 1, but Area 3 also brings a higher current change rate lift after passing through Area 2. Therefore, the intersection of Areas 1 and 2 is the best compromise point for efficiency and electrical stress.