A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process

• Published in: IEEE journal of solid-state circuits Vol. 59; no. 7; pp. 2185 - 2198
• Main Authors: Yoon, Dong-Hyun, Baek, Kwang-Hyun, Kim, Tony Tae-Hyoung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-07-2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accumulation; CMOS; Current sources; Decoding; Digital to analog converters; Direct-digital frequency synthesizer (DDS); Errors; Figure of merit; Frequency hopping; Frequency modulation; frequency synthesizer; Frequency synthesizers; nonlinear digital-to-analog converter (DAC); Nonlinearity; Power consumption; Power demand; signal-to-noise and distortion ratio; spurious-free dynamic range (SFDR); Synthesis; Synthesizers; Thermometers; Thermometry; Time-frequency analysis; Voltage-controlled oscillators; Wireless communications
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2023.3341040

Direct-digital frequency synthesizers (DDSs) are highly attractive in wireless communications because of their fast frequency hopping characteristics. Generally, DDSs adopt truncation and thermometer decoding for high-frequency resolution and monotonicity, respectively. However, the truncation causes poor spectral purity due to periodical errors in phase accumulation. Also, the thermometer decoding scheme of digital-to-analog converter (DAC) requires many current sources, which creates large parasitic components and nonlinearity. This article presents several techniques for addressing the above challenges. First, a fixed-weight decoder (FWD) with an auxiliary DAC is proposed to remove the truncation spur in the phase accumulation. Since FWD controls the amplitude regardless of the phase, it removes the periodic errors without significant power increment. Second, the proposed tristate decoding scheme reduces the number of current sources to reduce timing mismatches and capacitances. Finally, a fine current source reusing technique is developed to reduce the number of current sources and power consumption. The proposed DDS was fabricated in a 65-nm CMOS technology. The worst spurious-free dynamic range (SFDR) is 57.35 dBc at 2.5 GHz with a power consumption of 104 mW. The measured figure of merit is 18 124 GHz<inline-formula> <tex-math notation="LaTeX">\cdot 2^{\mathbf {(SFDR/6)}} </tex-math></inline-formula>/W.