Real-Time Event Handling and Preemptive Hardware RTOS Scheduling on a Custom CPU Implementation

• Published in: Canadian journal of electrical and computer engineering Vol. 43; no. 4; pp. 364 - 373
• Main Authors: Zagan, Ionel, Gaitan, Vasile Gheorghita
• Format: Journal Article
• Language: English
• Published: Montreal IEEE Canada 01-01-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Central processing units; Circuits; CPUs; Event handling; Field programmable gate arrays; Field-programmable gate arrays (FPGAs); Hardware; Microprocessors; pipeline processing; Pipelines; Preempting; Real time; Real-time systems; real-time systems (RTSs); Registers; scheduling; Switches; Synchronism; Task analysis; Task scheduling
• DOI: 10.1109/CJECE.2020.3005360
• EISSN: 2694-1783
• ISSN: 0840-8688

The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.