Novel design for testability schemes for CMOS ICs

• Published in: IEEE journal of solid-state circuits Vol. 25; no. 5; pp. 1239 - 1246
• Main Authors: Favalli, M., Olivo, P., Damiani, M., Ricco, B.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-10-1990; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit faults; Circuit testing; CMOS logic circuits; Design for testability; Electrical fault detection; Electronics; Exact sciences and technology; Fault detection; Integrated circuits; Integrated circuits by function (including memories and processors); Logic testing; Power supplies; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Steady-state; Voltage; Design; Improvement; Complementary MOS technology; Test; Integrated circuit; Delay time; Performance; Defect detection
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.62148

The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). Two techniques are proposed for detecting analog faults, particularly those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. Involving the conversion of analog faults into stuck-ats and the use of distributed testing logic, these techniques are shown to avoid the drawbacks of previous solutions. A method is proposed for online detection of delay faults, so far not yet considered in the context of design-for-testability. All the proposed techniques require little extra hardware and lead to minimal performance degradations.< >