Design of high-speed, low-power non-volatile master slave flip flop (NVMSFF) for memory registers designs

• Published in: Applied nanoscience Vol. 13; no. 8; pp. 5369 - 5378
• Main Authors: Muthappa, K. A., Nisha, A. Sahaya Anselin, Shastri, Rajveer, Avasthi, Vinay, Reddy, Pundru Chandra Shaker
• Format: Journal Article
• Language: English
• Published: Cham Springer International Publishing 01-08-2023; Springer Nature B.V
• Subjects: Arrays; Chemistry and Materials Science; Circuits; Design; Electron spin; Electrons; Energy dissipation; High speed; Materials Science; Membrane Biology; Nanochemistry; Nanotechnology; Nanotechnology and Microengineering; Original Article; Potential energy; Power management; Semiconductor devices; Spintronics; Torque; Tunnel junctions; Magnetic tunnel junction (MTJ); CMOS; Verilog-A model; Non-volatile master slave flip flop (NVMSFF); Spin orbit torque (SOT); Spintronic
• ISSN: 2190-5509; 2190-5517
• DOI: 10.1007/s13204-023-02814-5

High-speed and low-power area-efficient memory solutions are in high demand in today’s smart and internet environment. To program and store data and its associated information, it has grown as a fantastic concept to replace charge in semiconductor devices with electron spin. By further eliminating power dissipation, this leads to the development of “green electronics,” a field of technology that is both energy and chip space efficient. A sort of spintronic device created for potential energy-efficient applications is the magnetic tunnel junction (MTJ) device controlled by spin orbit torques (SOTs). A three-terminal MTJ device with perpendicular to the plane magnetization may operate more quickly and efficiently thanks to the available spin orbit torques (PMTJ). The design of a novel modified non-volatile master slave flip flop (NVMSFF) for register memory array architectures is presented in this study. It is low-power, high-speed, and area-efficient. The NVMSFF design uses a hybrid approach that combines CMOS 45 nm technology with a Verilog-A Model-based SOT-PMTJ circuit that uses spintronics. Additionally, the planned NVMSFF and current NVSFF were used in the design of the 4 × 4 and 8 × 8 memory arrays. The suggested updated NVMSFF was shown to have a lower latency, use less space, and dissipate less power. Additionally, it was discovered that Designed Memory arrays were space and energy efficient.