An FPGA/MPSoC Based Low Latency Onboard SAR Processor

• Published in: 2021 IEEE International Geoscience and Remote Sensing Symposium IGARSS pp. 5159 - 5162
• Main Authors: Breit, Helko, Mandapati, Srikanth, Balss, Ulrich
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11-07-2021
• Subjects: Data processing; EO-ALERT; FPGA; MPSoC; on-board processing; Processor scheduling; Program processors; Prototypes; Radar polarimetry; SAR; Sea state; Spaceborne radar; TerraSAR-X
• ISSN: 2153-7003
• DOI: 10.1109/IGARSS47720.2021.9553539

This paper describes the concept and prototype implementation of a low latency spaceborne onboard Synthetic Aperture Radar (SAR) processor runing on a Multi-Processor-System-On-Chip (MPSoC) computing device combining an ARM processor and a Field-Programmable-Gate-Array (FPGA). The SAR processor is designed to generate SAR imagery from TerraSAR-X stripmap data for subsequent ship detection and sea state determination. Low latency data processing is a key development goal. Currently, a raw data block of 8\mathrm{k}\times 32\mathrm{k} samples, covering 375 km 2 to 500 km 2 , is focused on the hardware within 4 s. Together with an attached level-2 ship detection, wind, and sea state processor, running on the same device, a SAR data processing chain for generation of maritime alerts is formed. This chain is part of a larger prototype system being developed in the frame of the H2020 EO-ALERT project which further comprises an optical data chain, data compression/encryption, and scheduling on multiple reconfigurable MPSoC boards.