Determining the Zero-Temperature-Coefficient Point From Device Simulation to Circuit for Improving Temperature Variation Immunity

• Published in: IEEE transactions on electron devices Vol. 70; no. 3; pp. 1 - 7
• Main Authors: Chen, Wangyong, Zheng, Mingyue, Lyu, Yaoyang, Cai, Linlin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit design; Circuit reliability; Coefficient of variation; Delays; Digital circuits; Digital electronics; Effective current; Frequency variation; Gallium arsenide; High temperature effects; Immunity; Integrated circuit modeling; Integrated circuits; nanosheet (NS); self-heating; Simulation; Slew rate; temperature immunity; Trajectory; Voltage; zero-temperature delay (ZTD)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2023.3234897

Thermal issue emerges as one of the critical reliability concerns in integrated circuit design, especially for advanced technology. To improve the temperature immunity and reduce the thermal-related timing guard bands in digital circuits, in this work, we offer a new insight into the zero-temperature-coefficient (ZTC) based design strategy featuring minimizing the temperature-induced delay variation. An effective current-based method to facilitate the ZTC point (<inline-formula> <tex-math notation="LaTeX">\textit{V}_{\text{ZTC}}</tex-math> </inline-formula>) determination for standard cells is developed, which is demonstrated on advanced gate-all-around (GAA) nanosheet (NS) FETs from 300 to 425 K using the calibrated TCAD simulation. The <inline-formula> <tex-math notation="LaTeX">\textit{V}_{\text{ZTC}}</tex-math> </inline-formula> dependencies on the signal input slew rate, output capacitance, and self-heating effects (SHEs) are further investigated from the perspective of the effective current by tracing the voltage trajectory. The mixed-mode TCAD simulation results show that the frequency variation of ring oscillator (RO) reduces nearly ten times when operating near <inline-formula> <tex-math notation="LaTeX">\textit{V}_{\text{ZTC}}</tex-math> </inline-formula> and great power-performance trade-offs can also be achieved. The <inline-formula> <tex-math notation="LaTeX">\textit{V}_{\text{ZTC}}</tex-math> </inline-formula> determination for standard cells combined with the compensation effect among different standard cells benefits selecting the optimal zero-temperature-delay (ZTD) point in the target path, thereby helping to implement a robust digital design against temperature variation.