Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models

• Published in: Sixth international symposium on quality electronic design (isqed'05) pp. 476 - 481
• Main Authors: Yuanzhong Zhou, Connerney, D., Carroll, R., Luk, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Availability; Bipolar transistors; Circuit simulation; Convergence; Electrostatic discharge; Equations; Hardware design languages; MOSFETs; Resistors; Silicon
• ISBN: 9780769523019; 0769523013
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2005.81

A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. No external current source, which is essential in most publicly reported macro models, is included since both BSIM3vs and VBIC have formulations built in to model the relevant effects. The simplicity of the presented macro model makes behavior languages, such as Verilog-A, and special ESD equations not necessary in model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. Measurement and simulation of the new approach indicates that good silicon correlation can be achieved.