The Optimal Choice of High Pin Count ASIC Packages

• Published in: Microelectronics international Vol. 6; no. 2; pp. 13 - 16
• Main Authors: Gustafsson, K, Andersson, U, Ek, S, Liljestrand, L.-G
• Format: Journal Article
• Language: English
• Published: MCB UP Ltd 01-02-1989
• ISSN: 1356-5362
• DOI: 10.1108/eb044366

The choice of high pin count ASIC packages has a major impact on the total cost and performance of the whole packaging system. Six different types of ASIC packages have been compared with respect to production aspects, availability, reliability, thermal and electrical properties and cost. Recommendations for the proper choice of packages for different types of applications are given. All packages have been directly assembled to PWBs in order to study problems with handling, solder process, testing and repairability. Some of the assembled packages have been temperature cycled in order to test the solder joint reliability. The pin grid array packages are the most frequently used high pin count packages today. However, they are expensive and through-hole mounting reduces the routing capability of the board. Pad area array packages are a hermetic alternative with a lower price for the package as well as very good thermal and electrical properties, but they need to be mounted on expensive PWBs. Another surface mountable package which is hermetic is the ceramic leaded chip carrier with fine lead pitch. This package is even more expensive than the pin grid array package and is difficult to handle. In the future, non-hermetic alternatives will probably predominate. Plastic quad flat pack and TapePak can be used below 160-180 leads, while direct assembled TAB would be the best alternative for very high pin counts. Before one can use non-hermetic packages in telecom products, a large qualification programme must be performed to evaluate the long-term reliability.