Scalable Substrate Current Model for LDMOS Transistors Based on Internal Drain Voltage

• Published in: IEEE transactions on electron devices Vol. 69; no. 8; pp. 4095 - 4101
• Main Authors: Kaushal, Kumari Neeraj, Dan, Virender, Mohapatra, Nihar R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-08-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Compact model; Data models; drift region; Electric potential; impact ionization (II); internal drain voltage; laterally diffused MOS (LDMOS); Logic gates; Mathematical models; Modulation; MOS devices; Semiconductor device modeling; Semiconductor devices; space charge modulation (SCM); substrate current; Substrates; Transistors; Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3179456

In this work, a scalable robust substrate current model for laterally diffused MOS (LDMOS) transistors is presented. The model is created in two stages. First, a model for intrinsic drain voltage, which accurately captures the modulation of intrinsic drain voltage with applied gate and drain voltages, is developed. This model is then used to derive an expression for the substrate current. The accuracy of the substrate current model is verified by comparing it with the data measured from LDMOS transistors with different device dimensions. The model accurately captures the modulation of substrate current with bias voltages and shows excellent scalability. Different LDMOS designs are also suggested to reduce the substrate current at the same OFF-state breakdown voltage.