2.8-GB/s-write and 670-MB/s-erase operations of a 3D vertical chain-cell-type phase-change-memory array

• Published in: 2015 Symposium on VLSI Technology (VLSI Technology) pp. T92 - T93
• Main Authors: Kurotsuchi, K., Sasago, Y., Yoshitake, H., Minemura, H., Anzai, Y., Fujisaki, Y., Takahama, T., Takahashi, T., Mine, T., Shima, A., Fujisaki, K., Kobayashi, T.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: JSAP 01-06-2015
• Subjects: Arrays; Bundling; Chains; Channels; Computer storage devices; Electrodes; Logic gates; Metal oxide semiconductors; Microprocessors; Resistance; Three dimensional; Throughput
• ISSN: 0743-1562; 2158-9682
• DOI: 10.1109/VLSIT.2015.7223705

A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition, CO 2 laser annealing enhances the drivability of a poly-Si cell MOS to 680 μA/μm to suppress energy loss in the cell MOS. In addition to write throughput, erase throughput is increased by erasing memory cells in a "bundle" by channel heating (called "bundle erase"). GeSbTe CVD with high uniformity is also developed.