10 GB/s bit-synchronizer circuit with automatic timing alignment by clock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

• Published in: IEEE journal of solid-state circuits Vol. 27; no. 10; pp. 1347 - 1352
• Main Authors: Wennekers, P., Novotny, U., Huelsmann, A., Kaufel, G., Koehler, K., Raynor, B., Schneider, J.
• Format: Journal Article
• Language: English
• Published: IEEE 01-10-1992
• Subjects: Bit rate; Circuits; Clocks; Gain measurement; Master-slave; Phase detection; Phase measurement; Sampling methods; Signal sampling; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.156436

A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are +or-54 degrees relative to the 'in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V.< >