Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance

Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance

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Bibliographic Details
Published in:30th European Solid-State Device Research Conference pp. 300 - 303
Main Authors: Bowman, K.A., Lihui Wang, Xinghai Tang, Meindl, J.D.
Format: Conference Proceeding
Language:English
Published: Editions Frontieres 2000
Subjects:
Circuit optimization
CMOS logic circuits
CMOS technology
Constraint optimization
Contracts
Mathematical model
Performance analysis
Power MOSFET
Threshold voltage
Tunneling
Online Access:Get full text
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Description
ISBN:9782863322482
2863322486
DOI:10.1109/ESSDERC.2000.194774