Scheduling Algorithm for Multi-Component Digital Systems to Minimize Dynamic Power

• Published in: Journal of applied sciences (Asian Network for Scientific Information) Vol. 15; no. 4; pp. 654 - 660
• Main Authors: Hassine, Siwar Ben Haj, Ouni, Bouraoui, Samaali, Hatem
• Format: Journal Article
• Language: English
• Published: 15-03-2015
• Subjects: Algorithms; Clocks; Digital systems; Dynamical systems; Dynamics; Power consumption; Reduction; Scheduling
• ISSN: 1812-5654; 1812-5662
• DOI: 10.3923/jas.2015.654.660

As embedded systems have become wide reaching technology, the need for better performance has been persisting. For that, researchers have made great effort to come up with new techniques in order to obtain a better performing system that consumes less power. From here, it comes the idea of developing a new scheduling algorithm that manages to achieve components, scheduling in order to reduce dynamic power consumption. The main purpose of that algorithm was to increase the latency of some components whenever it is possible without negatively influencing the dependency constraint. One of the main solutions to increase the latency of components was through decreasing frequency of their clocks. This decrease of the clock frequency brings about reduction in power consumption. To prove its efficiency, the new proposed algorithm has been tested at both levels: Simulation and physical one. In fact, design results have shown significant reduction in dynamic power.