Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck...

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Published in:Nanoscale research letters Vol. 5; no. 10; pp. 1654 - 1657
Main Authors: Jang, Moongyu, Park, Youngsam, Jun, Myungsim, Hyun, Younghoon, Choi, Sung-Jin, Zyung, Taehyoung
Format: Journal Article
Language:English
Published: United States New York : Springer-Verlag 18-07-2010
BioMed Central Ltd
SpringerOpen
Subjects:
Nanowire
nanowires
Seebeck coefficient
Silicon
Thermoelectric effect
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Abstract Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K² at room temperature.
AbstractList Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K² at room temperature.
Abstract Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.
Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and -94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K(2) at room temperature.
Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.
Author Jun, Myungsim
Choi, Sung-Jin
Park, Youngsam
Zyung, Taehyoung
Hyun, Younghoon
Jang, Moongyu
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BackLink https://www.ncbi.nlm.nih.gov/pubmed/21076666$$D View this record in MEDLINE/PubMed
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Snippet Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of...
Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of...
Abstract Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities...
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SubjectTerms Nanowire
nanowires
Seebeck coefficient
Silicon
Thermoelectric effect
Title Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process
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