Design Space and Variability Analysis of SOI MOSFET for Ultra-Low Power Band-to-Band Tunneling Neurons

• Main Authors: Sonawane, Jay, Patil, Shubham, Kadam, Abhishek, Singh, Ajay Kumar, Lashkare, Sandip, Deshpande, Veeresh, Ganguly, Udayan
• Format: Journal Article
• Language: English
• Published: 30-11-2023
• Subjects: Physics - Applied Physics
• DOI: 10.48550/arxiv.2311.18577

Large spiking neural networks (SNNs) require ultra-low power and low
variability hardware for neuromorphic computing applications. Recently, a
band-to-band tunneling-based (BTBT) integrator, enabling sub-kHz operation of
neurons with area and energy efficiency, was proposed. For an ultra-low power
implementation of such neurons, a very low BTBT current is needed, so
minimizing current without degrading neuronal properties is essential. Low
variability is needed in the ultra-low current integrator to avoid network
performance degradation in a large BTBT neuron-based SNN. To address this, we
conducted design space and variability analysis in TCAD, utilizing a
well-calibrated TCAD deck with experimental data from GlobalFoundries 32nm
PD-SOI MOSFET. First, we discuss the physics-based explanation of the tunneling
mechanism. Second, we explore the impact of device design parameters on SOI
MOSFET performance, highlighting parameter sensitivities to tunneling current.
With device parameters' optimization, we demonstrate a ~20x reduction in BTBT
current compared to the experimental data. Finally, a variability analysis that
includes the effects of random dopant fluctuations (RDF), oxide thickness
variability (OTV), and channel-oxide interface traps DIT in the BTBT, SS, and
ON regimes of operation is shown. The BTBT regime shows high sensitivity to the
RDF and OTV as any variation in them directly modulates the tunnel length or
the electric field at the drain-channel junction, whereas minimal sensitivity
to DIT is observed.