A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

• Main Authors: Brüderle, Daniel, Petrovici, Mihai A, Vogginger, Bernhard, Ehrlich, Matthias, Pfeil, Thomas, Millner, Sebastian, Grübl, Andreas, Wendt, Karsten, Müller, Eric, Schwartz, Marc-Olivier, de Oliveira, Dan Husmann, Jeltsch, Sebastian, Fieres, Johannes, Schilling, Moritz, Müller, Paul, Breitwieser, Oliver, Petkov, Venelin, Muller, Lyle, Davison, Andrew P, Krishnamurthy, Pradeep, Kremkow, Jens, Lundqvist, Mikael, Muller, Eilif, Partzsch, Johannes, Scholze, Stefan, Zühl, Lukas, Mayr, Christian, Destexhe, Alain, Diesmann, Markus, Potjans, Tobias C, Lansner, Anders, Schüffny, René, Schemmel, Johannes, Meier, Karlheinz
• Format: Journal Article
• Language: English
• Published: 21-07-2011
• Subjects: Quantitative Biology - Neurons and Cognition
• DOI: 10.48550/arxiv.1011.2861

Biol Cybern. 2011 May;104(4-5):263-96 In this paper we present a methodological framework that meets novel
requirements emerging from upcoming types of accelerated and highly
configurable neuromorphic hardware systems. We describe in detail a device with
45 million programmable and dynamic synapses that is currently under
development, and we sketch the conceptual challenges that arise from taking
this platform into operation. More specifically, we aim at the establishment of
this neuromorphic system as a flexible and neuroscientifically valuable
modeling tool that can be used by non-hardware-experts. We consider various
functional aspects to be crucial for this purpose, and we introduce a
consistent workflow with detailed descriptions of all involved modules that
implement the suggested steps: The integration of the hardware interface into
the simulator-independent model description language PyNN; a fully automated
translation between the PyNN domain and appropriate hardware configurations; an
executable specification of the future neuromorphic system that can be
seamlessly integrated into this biology-to-hardware mapping process as a test
bench for all software layers and possible hardware design modifications; an
evaluation scheme that deploys models from a dedicated benchmark library,
compares the results generated by virtual or prototype hardware devices with
reference software simulations and analyzes the differences. The integration of
these components into one hardware-software workflow provides an ecosystem for
ongoing preparative studies that support the hardware design process and
represents the basis for the maturity of the model-to-hardware mapping
software. The functionality and flexibility of the latter is proven with a
variety of experimental results.